An exemplary embodiment of the present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device including a buried gate.
In a fabricating process for a small DRAM, such as a 60 nm DRAM, it is helpful to form a buried word line in order to increase the degree of integration of transistors in a cell, simplify a fabricating process, and improve a device property such as current leakage property.
In general, a trench is formed and a word line is buried in the trench to form a buried word line. This buried word line forming method, according to the related art, has the following advantages. The interference between a bit line and a word line is minimized, the number of stacked films is reduced, and a refresh property is improved by reducing overall capacitance of cells.
FIG. 1 is a cross-sectional view illustrating a semiconductor device employing a conventional buried gate.
Referring to FIG. 1, the conventional semiconductor device includes a semiconductor substrate 11 where an active region 13 is defined by a device isolation layer 12, a trench 14 formed by simultaneously etching the active region 13 and the device isolation layer 12, a buried gate 16 filling a part of the trench 14, and a gap-fill layer 17 formed on the buried gate 16 to gap-fill the rest of the trench 14. A gate dielectric layer 15 is formed between the buried gate 16 and the trench 14.
In the prior art illustrated in FIG. 1, the gap-fill layer 17 gap-fills on the upper side of the buried gate 16 to prevent the buried gate 16 from being oxidized and degraded in a subsequent heating process. In the prior art illustrated in FIG. 1, the gap-fill layer 17 uses a silicon oxide layer, and the buried gate 16 uses a metal gate.
However, since a subsequent stacked layer is formed after forming the buried gate 16, the buried gate 16 may be degraded during a subsequent heating process, such as an oxidation process.
Further, a contact hole 19 is formed by etching an inter-layer dielectric layer 18 in a state that no structure is formed after forming the stacked layer of the buried gate 16 and the gap-fill layer 17. As a result, it is difficult to secure a process margin for forming a contact. Since the contact hole 19 is formed through the gap-fill layer 17 when an overlay is missed (see the reference numeral ‘20’) a short between the buried gate 16 and the contact can occur.